One of the main objectives of this case study is to capture the best practice from chip design, e.g. which tool to use for certain processes and tasks, and how to use the tool effectively.This will necessitate understanding the relationship between user context and usage patterns; and also understanding the informal knowledge processes comprising the various paths through the toolsets which designers use. The other main objective is to use ACTIVE technology to support Cadence engineers when undertaking customer projects.

Initially the users will be 130 Cadence engineers, of whom 40% are electronic engineers and the remaining 60% are software and customer process engineers. Cadence engineers are organised in teams. Teams of 2 to 5 people design processes and design support teams of 20 people undertake engineering design. Potential the users can expand to design engineering teams at Cadence’s customers, totalling many thousands of engineers.

A typical design process at Cadence consists of between 10 and 15 steps and requires about 800 ontological instances. A design process at one of the clients consists of 10,000 core design steps and around 100,000 steps in all. The data will be the logfiles from the design tools, which will provide information about design tool usage, e.g. in which combination design tools are applied.

The system, as chip designers typically use, will be a combination of a UNIX system for development and a PC for office applications.  For development a range of tools is used, including emacs and vi.  For standard office applications Mozilla, and both Open Office and MS Office are used.

The participants in the ACTIVE project will be part of the Cadence engineering team.  They will act as the support team for their colleagues. Cadence’s VCAD team is constantly looking for ways to improve the productivity of its own design engineers and those of our services customers, and any automation and improvement of this is completely aligned to our organisational mission.

Chip design is highly complex and demands highly trained specialists. As such, they are motivated to use tools which improve the speed of the design process or the quality of the final product. As with the other two case studies, the system will need to have low barriers to entry and exhibit clear benefits to be accepted.  This is particularly the case for Cadence engineers working under pressure with customers.

The case study will enable dissemination activities using a range of events and publications within the chip design industry, of which Cadence is a market leader. Cadence is active in many countries worldwide.  Dissemination will initially take place in many EU countries and later in China, India and other Asian countries.

Cadence is actively involved in standardisation in area of design software, e.g. data formats for exchanging data.  Standards fora will therefore be another channel for dissemination activities.

Ontologies are already being used in Cadence systems.  The T-Box is being used to describe design processes and the A-Box to design concrete processes and tasks.  Involvement in the ACTIVE project will enhance the use of semantic technology.  One aim is to use an ontology as a “formal specification” to describe design processes in a consistent manner for the sector. Formal semantics will be combined with the use of Web2.0 technology, in particular the tagging of design processes and tasks.

Design processes are currently manually defined, and ACTIVE technology will be used to enhance this by learning processes.  To-date the effort for describing tasks and processes has been underestimated.  The work of WP4 in understanding the economic aspects of Web2.0 and semantic technologies will be applicable here. The use of context to better understand the user’s current requirements is seen as an important add-on to current functionality.